In the fabrication process of a semiconductor device, in order to reduce the surface area of the semiconductor device, the flip-chip bonded stacked chips technology is developed, which uses copper bumps or solder bumps as bonding points between the bonded chips for signal transmission. FIG. 1A is a schematic showing the cross-sectional view of a semiconductor chip with copper bumps in a prior art, which comprises a substrate 101, a metal layer 103, a metal bump 105, and an electronic device 113. The electronic device 113 is formed on the front-side of the substrate 101. The metal layer 103 is formed on the front-side of the substrate 101 and connected to the electronic device 113. The metal bump 105 is formed on the metal layer 103. FIG. 1B is a schematic showing the cross-sectional view of flip-chip bonded stacked chips with copper bumps in a prior art, which is similar to the structure shown in FIG. 1A, except that an upper chip 135 is stacked on the metal bumps 105. The metal bumps 105 are connected to the upper chip 135. The electric signal from the electronic device 113 on the substrate 101 can be transmitted through the metal bumps 105 to the upper chip 135. A module substrate 133 is disposed under the substrate 101, and at least one bonding wire 137 is disposed on the module substrate 133. The electric signal from the electronic device 113 can be further transmitted through the bonding wire 137 to the module substrate 133.
Although the abovementioned design can form flip-chip bonded stacked chips, the density of the integration of the devices are limited, and thus the reduction of the chip size is restricted. The signal transmission speed can not be significantly increased, and therefore the electric power consumption of the circuit remains high. It is not possible to form more than two flip-chip bonded stacked chips.
To solve the abovementioned problems, the present invention provide a stacked structure including at least one semiconductor chip with substrate via holes and metal bumps to achieve heterogeneous integration, to improve the integration of the devices, to reduce the chip size, to increase the signal transmission speed, to lower the electric power consumption, and to reduce the material cost.